1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to adjustment of a delay lock loop.
2. Description of Related Art
Many integrated circuit systems use a clock to synchronize communication between various components of the system. For example, a processor in communication with a device, such as a memory, may use a clock signal to assure that data is made available from the memory at a time when the processor is ready to receive it. However, due to differences in propagation and response times in the processor and memory, there may be time differences between the clock signal as perceived in the processor and the memory. In order to compensate for these differences, a delay may be applied to a copy of the clock signal sent to the memory in order.
The optimum delay depends on various environmental and physical parameters and/or characteristics such as supply voltages, and the structures of the components resulting from production of the components and installation of these components in various packages and/or devices. For example, two integrated circuit systems assembled from the components meeting identical specifications may require different delays and these delays may change over time. Optimum delays are, therefore typically determined by the system components in real time. This determination is sometimes made using a delay lock loop (DLL). A DLL uses a feedback circuit to identify a preferred delay and uses the identified delay to delay an output signal (e.g., memory clock) relative to an input system (e.g., system clock).
A DLL may operate by incrementally increasing a delay until a preferred delay is found. A disadvantage of this approach is that the precision of the preferred delay is dependent on the size of the incremental increase. A greater precession requires a smaller increment. However, a smaller increment results in a longer time before a preferred delay can be found. This may be a problem in some systems. What is needed is an efficient method for more quickly determining the preferred delay for a DLL in a integrated circuit system.